NDMs consolidate logical timing data ( .db ), physical layout views, abstraction layers, and parasitic models into a single, unified library file.
# Define logical and physical reference libraries set_app_var search_path ". ./libs/tech ./libs/logical" set_app_var target_library "core_typ_1v1.db" set_app_var link_library "* core_typ_1v1.db macro_typ_1v1.db" # Create or open the working database container # For Classic ICC (Milkyway): create_mw_lib my_design_lib.mw -technology tech_file.tf -mw_reference_library std_cell_lib macro_lib open_mw_lib my_design_lib.mw # Import the structural netlist and bind constraints import_designs my_chip.v -format verilog -top my_chip read_sdc my_constraints.sdc Use code with caution. Step 2: Floorplanning & Design Planning synopsys icc user guide pdf
Load libraries and design ( create_mw_lib , import_designs ). Floorplan: Perform create_floorplan and place_opt . Clock Tree: Run clock_opt . Route: Run route_opt . NDMs consolidate logical timing data (